/*--------------------------------------------------
file name  : pkt_if.sv
created    : 2025/10/26 19:45:32
description: 
notes      : 
author     : yyrwkk
--------------------------------------------------*/
interface pkt_if( input clk , input rst_n ) ;

    logic [(`PKT_DATA_WIDTH -1):0]   data   ;
    logic                            sop    ;
    logic                            eop    ;
    logic                            vld    ;

    clocking drv@(posedge clk) ;
        default input #1ps output 1ps;
        output data ;
        output sop  ;
        output eop  ;
        output vld  ;
    endclocking

    clocking mon@(posedge clk);
        default input #1ps output 1ps;
        input  data ;
        input  sop  ;
        input  eop  ;
        output vld  ;
    endclocking

endinterface
